1. Field of the Invention
The present invention relates to hierarchical specification and modeling of scheduling in system-level simulations of consumer embedded systems.
2. Background
The design of consumer embedded systems today is changing dramatically as product time-to-market and life cycles shrink, and product requirements grow with the continuing merger of communication and computing. Software, once a minor aspect of a design, is beginning to dominate. The re-use of intellectual property has become mandatory, as no single company possesses all the expertise required to build tomorrow's converging products.
The Virtual Component Codesign (VCC) methodology, available from Cadence Design Systems, assignee of the present invention, is designed to address these concerns at the system level. VCC is a methodology that is paired with a set of tools and libraries for the evaluation, selection, integration, and specification of virtual components (intellectual property) for embedded systems design. Virtual components in this context include not only hardware and software behaviors, but hardware and software architectures as well.
Three major tasks comprise the design flow in VCC: Composing behavior, capturing architecture and mapping behavior onto architecture. Behavior in VCC is expressed as a discrete event network of blocks that pass high-level tokens. Architecture in VCC is expressed as a topology of hardware and software structures. Mapping in VCC is an assignment of behavior onto architectural structures.
The assignments in the mapping determine which behavioral blocks become hardware and which become software, and how communication between behaviors occurs. The assignment of multiple behavioral blocks to a single architectural resource is allowed and denotes sharing. For example, a single microcontroller, shared by all software behaviors, is quite common in most consumer embedded systems.
The VCC environment provides a comprehensive system-level design environment that allows the user to clearly differentiate between a behavior model, which identifies what the system does, and an architecture model, which identifies how the system is implemented. This clear differentiation between system function and architecture allows system designers to simulate the performance effects of a behavior running on a number of different architectures early in the design cycle.
The VCC environment is an environment in which the system designer works with graphical representations of virtual components, both functional and architectural. The VCC behavior diagram editor permits capturing the function of a system by creating a behavior diagram—a collection of functional models that are wired together.
In top-down design flow using the VCC environment, designers create behavioral models by a) placing an undefined block, b) specifying the interface and the design parameters, and c) generating a symbol for this block. Once the user specifies how this block is to be implemented, a window with a default template for the model's behavior is generated. In bottom-up design flows using the VCC environment, designers use the hierarchical behavior diagram editor to instantiate graphical symbols representing already existing behavioral models, and then create the interconnections between these symbols.
VCC provides the ability to import functional IP from a wide variety of sources into the VCC simulation environment and allows designers to simulate the complete functionality of heterogeneous systems. This simulation then can be used as an executable functional specification.
Using a VCC architecture diagram editor, designers capture the abstract target architecture onto which the system function will be mapped. Since it is a complete Co-design environment, the VCC environment supports essential architectural elements such as CPUs, DSPs, RTOSs, buses, memories, and dedicated hardware and software. To allow fast design evaluation, these architectural elements are modeled at a higher level of abstraction than implementation-level C or HDL.
A VCC mapping diagram editor enables designers to map system functionality onto target architectural platforms. This mapping defines candidate hardware and software partitions and helps to identify the custom hardware needed to complete the system design. Designers also use the mapping diagram editor to refine communication wires.
Once a mapping diagram is completed, the system designers can evaluate the mapped design using performance simulation, which is enabled by software estimation and performance parameters that are annotated within timing free functional models.
In VCC, performance simulation determines, for a particular mapped design, whether the timing of the system meets the user's requirements. If not, the user can map portions of the behavioral blocks to different architectural blocks, possibly causing their implementation to move between hardware and software. The design may be a system-on-a-chip with embedded processors, memories, and custom hardware, or it may be composed of discrete processors, memories and multi-function component chips.
When the design is at the fully refined level within VCC and its performance meets the system requirements, the user can export it as a software and hardware implementation. The hardware design will then be ready for HDL simulation, floor planning and logic synthesis. The software models will then be ready for linking to an RTOS (real-time operating system).
Software export of the user's application comprises configuring the selected RTOS for the chosen processor. This includes creating tasks, adding appropriate mechanisms for inter-task and intra-task communication, synthesizing static schedulers where multiple behaviors are mapped to the same task, configuring the RTOS scheduler, setting up interrupt handlers, and setting-up counters and timers.
To avoid situations where too many tasks are running on an RTOS (potentially resulting in unacceptably high-context switching overhead), the VCC environment allows the user to map multiple behavioral blocks to the same task. In this situation, VCC synthesizes a static scheduler, i.e., a simple sequential execution of the behaviors' run functions.
VCC also employs simulation to allow a designer to evaluate a mapping. Using simulation to evaluate a mapping requires the specification and modeling of the scheduling of shared architectural resources. Specifying proper scheduling for a design is critical because the scheduling materially affects the feasibility, quality, reliability, and cost of a design.
The present invention therefore resolves the issues of how to specify scheduling at the system level, and how to use such a specification in simulation and software implementation.